The long-awaited beta release of Vitis AI 5.1 from AMD has been announced, marking the beginning of a major architectural shift that significantly advances edge AI inference capabilities.
Vitis AI 5.1 introduces support for a new Neural Processing Unit (NPU) architecture, replacing the previous DPU (Deep Learning Processing Unit) and specifically targeting Versal AI Edge Series SoCs. This new architecture represents a critical step for embedded and real-time AI applications that require low latency and high energy efficiency. By combining AMD’s AI Engine (AIE) arrays with Programmable Logic (PL), the platform delivers not only higher performance but also efficiency-driven acceleration for both standard and custom neural network workloads.
The Vitis AI NPU IP operates as a general-purpose AI inference accelerator. Multiple neural network models can be loaded and executed concurrently on a single NPU. In addition, multiple NPU IP instances can be instantiated per device, and the NPU IP can be scaled in size to meet application-specific performance requirements.
Model Compilation Toolchain
Vitis AI Quantizer
Integrated as a component of TensorFlow or PyTorch, the Vitis AI Quantizer converts 32-bit floating-point weights and activations into narrower data types such as INT8. This significantly reduces computational complexity while maintaining minimal accuracy loss (typically around 1%).
Vitis AI Compiler
The Vitis AI Compiler transforms the quantized model into a highly efficient instruction set and dataflow representation. Leveraging the NPU IP’s multi-dimensional parallelism, the compiler performs multiple optimizations to maximize inference throughput and efficiency.
Model Deployment APIs
Vitis AI Runtime (VART)
VART provides a set of APIs that enable seamless integration of the NPU IP into software applications. With support for both C++ and Python APIs, VART greatly simplifies software integration while enabling hardware-agnostic execution. As a result, deploying new models does not require recompiling hardware or loading a new bitstream, dramatically shortening development cycles and accelerating time to market compared to traditional accelerator approaches.
For more information and project-specific support, you may contact the Empa R&D Center AI team or visit the relevant AMD web resources:
https://www.amd.com/en/developer/resources/vitis-ai.html
https://vitisai.docs.amd.com/en/latest/index.html
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The long-awaited beta release of Vitis AI 5.1 from AMD has been announced, marking the beginning of a major architectural shift that significantly advances edge AI inference capabilities.
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